1. Field of the Invention
The present invention is related to digital transmission of voice and data. More particularly, the invention removes jitter commonly found in repeater-transmitted digital signals.
2. Discussion of Related Art
Regenerative repeaters that provide some form of correction for high frequency timing errors, commonly referred to as jitter, are known. U.S. Pat. No. 4,054,747 describes means for correcting phase errors in transmitted data. Errors exceeding one unit interval produces a reset. U.S. Pat. No. 4,270,183 describes means for removing jitter from digital signals played back from a magnetic tape recording, in which many bits of data are offset by phase errors as a result of jitter.
In the '183 patent, data is clocked into a multi-part cascaded FIFO buffer in response to a coincidence of a given pulse of the data clock and a pulse from a fixed-frequency local clock. Data is output in response to a coincidence between local and given clock pulses. The dejitterizer's output rate is reset in response to a half-full buffer status detected by tapping the "input ready" line of a FIFO device in the middle of the buffer. The rate at which data is output as a serial bit stream is a function of the amount of data in the buffer at a given moment, to maintain adequate "head room" in the buffer.
Dejitterizers are particularly important in transmission networks where frequent amplification is required to maintain adequate signal levels, such as T4 fiber optic systems, and in longdistance data links generally. For T1 carrier applications, where the suggested maximum jitter offset is eight bits wide*, only one 64-bit FIFO device is required. However, when only one FIFO device is used in the buffer, instead of the multiple devices disclosed in the '183 patent, the input ready signal from the buffer device cannot be used to control the FIFO buffer because it only indicates when the buffer is full. Some other means for accurately determining the "half-full" status must be provided when using a single FIFO device. Also, if an up-down counter is used to determine buffer status some means must be found to prevent a simultaneous up and down count inputs to assure an accurate count, since the signals which clock the input and the output of the FIFO buffer are effectively asynchronous. FNT *(Reference: Bell Systems Technical Reference Section 3.6, paragraph 3, FIG. 2 (Terminal Jitter Tolerance Recommended Template))